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Newsgroups: comp.sys.apple2
Path: news.weeg.uiowa.edu!news.uiowa.edu!hobbes.physics.uiowa.edu!zaphod.mps.ohio-state.edu!uwm.edu!spool.mu.edu!agate!rsoft!mindlink!a3916
From: Clayten_Hamacher@mindlink.bc.ca (Clayten Hamacher)
Subject: Re: ZipGSX programming...(register info)
Organization: MIND LINK! - British Columbia, Canada
Date: Sat, 30 Jan 1993 01:12:55 GMT
Message-ID: <20249@mindlink.bc.ca>
Sender: news@deep.rsoft.bc.ca (Usenet)
Lines: 79
I asked questions recently regarding the zip and how to control it and
received a bunch of mail, Zippy (GREAT program), and the following list of
registers and info on how to change them...
I can't remember who sent it to me as it was a binscii'd file and I didn't
save the message it unpacked from.
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ZipChip GS Special Registers Ex ZIP Technology, 12 October 1990
Registers must be unlocked before they can be accessed (see $C05A). Locking
them will re-enable the annunciators.
Writing to any I/O location $C058-$C05F (whether registers are locked or
unlocked) will reset delay in progress.
$C058 R No operation
$C058 W Write any value to force poweron/reset bit to COLD (forces next
reset to restore ZIP registers to defaults/switch settings).
$C059 R/W 76543210
*....... Bank Switch Language Card cache disable=1/enable=0?
.*...... Paddle delay (5 ms) disable=0/enable=1 $C070/$C020
..*..... External delay (5 ms) disable=0/enable=1
...*.... Counter delay (5 ms) disable=0/enable=1 $C02E/$C07E
....*... CPS follow disable=0/enable=1
.....*.. Last Reset warm? READ ONLY
......*. Hardware DMA READ ONLY
.......* non-GS (0)/GS (1) READ ONLY
$C05A R 76543210
****.... Current ZIP Speed, 0=100%, 1=93.75%, ..., F=6.25%
....1111
$C05A W Write values as follows:
$5x Unlock ZIP registers (must write 4 times)
$Ax Lock ZIP registers
other Force ZIP to follow system clock (i.e. disable card)
$C05B R 76543210
*....... 1msclk - clock with 1 ms period
.*...... cshupd - Tag data at $C05F updated (read $C05F to reset)
..*..... Bank Switch Language Card cache (0), don't (1)
...*.... Board disable - 0=enabled, 1=disabled
....*... delay in effect (0=ZIP, 1=Slow)
.....*.. rombank (0/1) - not in development version
......** Cache RAM size (00=8k, 01=16k, 10=32k, 11=64k)
$C05B W Write any value to force ZIP to current speed (i.e. enable card)
$C05C R/W 76543210
*******. Slot 7-1 delay enable (all slots 52-54 ms)
.......* Speaker delay enable (5 ms)
$C05D R Current 65816 bank
$C05D W 76543210
****.... Set ZIP speed, 0=100%, 1=93.75%, ..., F=6.25%
....**** Don't care
$C05E R Read last Tag data written and force the next write to create a
trash
tag value.
$C05E W No operation
$C05F R Read last Tag data written and reset cshupd. Note: apparently any
write to a ZIP register (unlocked) will clear cshupd, but cshupd says that
this
location must be read.
$C05F W No operation
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Clayten_Hamacher@Mindlink.bc.ca Land of the rising snow.