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Subject: Re: //e, //c, //gs Questions From: dempson@actrix.gen.nz (David Empson) Date: Fri, Oct 23, 1998 23�2 � Message-id: <1dhewzu.15dprdo18zz5poN@dempson.actrix.gen.nz> Mitchell Spector <spec@vax2.concordia.ca> wrote: > In article Maynard Lilac <texicus@hotmail.com> writes... > >Which of these systems allow memory expansion? > > All do. The IIe and IIc work with bank-switching (read in small > 64K chunks at a time) or Slinky-type RAM boards (reads bytes in a > sequential order, one byte at a time I believe; Hence the nickname > "Slinky" since it slinks byte by byte like a slinky toy going down > stairs--step by step without jumping around. I may be off here, > this is just my understanding off how the two work). Exactly right in the case of Slinky cards (one byte read/write data register with three byte auto-incrementing address register). The IIe auxiliary slot (and IIc equivalent) bank-switching cards do switch entire 64K banks over, but this only affects the "auxiliary memory" area, so it interacts with the built-in bank switching mechanisms (16K language card split into 4K and 12K banks switched at the same time as stack and zero page, separate read/write bank select for the main 48K area). It is generally necessary to replicate bank-switching code through all banks, or avoid using some areas of each bank (e.g. the language card and zero page/stack space), making it less efficient than the slinky cards. > Souped up IIe and IIc systems often had anywhere from 256K to 1 MB added, > or in rare cases, up to 3 MB. In theory, both the auxiliary slot and slinky cards could support up to 16 MB of RAM, but I also never heard of anything larger than 3 MB, and then only with piggy-back cards. > The Apple IIgs used a different, more direct memory addressing > technique because it used a 65C816 (it's address bus is 24-bit, or > 16,777,216 bytes, whereas the 65C02 had a 16-bit address bus, or > only 65,536 bytes). I think it used linear addressing, though not > sure if it saw memory in chunks or as one big piece, probably the > former based on what I know. I'll let a programmer step in here. :) (Steps up to the podium.) The IIgs address space is linear and any location can be directly addressed by selected instructions. It is organised logically into 64K banks, but this is only significant for some areas: - Code cannot cross 64K bank boundaries without a far jump, call, return, or interrupt. - "Absolute" address modes (two byte address) use a data bank register, which sets the starting bank for being accessed (indexing may cross the bank boundary). - Stack and zero page accesses are restricted to bank 0 (and indexing wraps around within this bank). - Emulation mode is even further restricted to bank 0 (code cannot be executed outside bank 0 unless interrupts are locked out). - Interrupt handlers and vectors must be in bank 0 (but the handler can use code in other banks). > The IIgs had either 256K or 1 MB+ built-in, and could be expanded > up to 8 megabytes in total (through plug-in boards that used DRAM, > in either ZIP/SIP and DIP packages, or SIMMs). (Pedantic mode on.) 8.125 MB, to be precise (8 MB of "fast" RAM plus 128 KB of "slow" RAM), assuming you don't count nonstandard additions like RAM-based ROM disks, which could add up to a further 768 KB in a ROM 3 or 896 KB in a ROM 1, though not for general program use. (I have a depopulated OctoRAM ESP, which puts 512KB of RAM into banks $F0 through $F7.) -- David Empson dempson@actrix.gen.nz Snail mail: P.O. Box 27-103, Wellington, New Zealand