💾 Archived View for bbs.geminispace.org › s › FPGA › 18960 captured on 2024-08-31 at 15:43:18. Gemini links have been rewritten to link to archived content
⬅️ Previous capture (2024-08-19)
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I thought I'd swipe a UART from some other project, but they are all horribly written by engineering students or maybe ChatGPT -- pages of state machines just to transmit!
So I rigged up a shift register to spit out serial. The core is 5 slices. Plus the timing generator to set the baud rate.
It took me way too long, but I am getting my verilog legs back.
https://tildegit.org/stack/Tangnano9K-UART-TX
Aug 04 · 4 weeks ago · 👍 norayr