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<head><title>PC-GPE on the Web</title></head><body><H1 align=center>PC-GPE on the Web</H1><p align=center><p><hr><pre> ��������������������������������������������������������Ŀ � Programming the Intel 8253 Programmable Interval Timer � ���������������������������������������������������������� Written for the PC-GPE by Mark Feldman e-mail address : u914097@student.canberra.edu.au myndale@cairo.anu.edu.au �������������������������������������������Ŀ � THIS FILE MAY NOT BE DISTRIBUTED � � SEPARATE TO THE ENTIRE PC-GPE COLLECTION. � ��������������������������������������������� ����������������������������������������������������������������������������� � Disclaimer � �������������� I assume no responsibility whatsoever for any effect that this file, the information contained therein or the use thereof has on you, your sanity, computer, spouse, children, pets or anything else related to you or your existance. No warranty is provided nor implied with this information. ����������������������������������������������������������������������������� � Introduction � ���������������� The PIT chip has 3 channels, each of which are responsible for a different task on the PC: Channel 0 is responsible for updating the system clock. It is usually programmed to generate around 18.2 clock ticks a second. An interrupt 8 is generated for every clock tick. Channel 1 controls DMA memory refreshing. DRAM is cheap, but it's memory cells must be periodically refreshed or they quickly lose their charge. The PIT chip is responsible for sending signals to the DMA chip to refresh memory. Most machines are refreshed at a higher rate than neccesary, and reprogramming channel 1 to refresh memory at a slower rate can sometime speed up system performance. I got a 2.5 MHz speed-up when I did it to my 286, but it didn't seem to work on my 486SUX33. Channel 2 is connected to the speaker. It's normally programmed to generate a square wave so a continuous tone is heard. Reprogramming it for "Interrupt on Terminal Count" mode is a nifty trick which can be used to play 8-bit samples from the PC speaker. Each channel has a counter which counts down. The PIT input frequency is 1193181 ($1234DD) Hz. Each counter decrements once for every input clock cycle. "Terminal Count", mentioned several times below, is when the counter reaches 0. Loading the counters with 0 has the same effect as loading them with 10000h, and is the highest count possible (approx 18.2 Hz). ����������������������������������������������������������������������������� � The PIT Ports � ����������������� The PIT chip is hooked up to the Intel CPU through the following ports: ���������������������������������������Ŀ � Port Description � ���������������������������������������Ĵ � 40h Channel 0 counter (read/write) � � 41h Channel 1 counter (read/write) � � 42h Channel 2 counter (read/write) � � 43h Control Word (write only) � ����������������������������������������� ����������������������������������������������������������������������������� � The Control Word � �������������������� �������������������������������Ŀ � 7 � 6 � 5 � 4 � 3 � 2 � 1 � 0 � ��������������������������������� ����� ����� ��������� ��� BCD 0 - Binary 16 bit � � � 1 - BCD 4 decades ����������������������Ŀ � � � Select Counter � � ����������� Mode Number 0 - 5 � 0 - Select Counter 0 � � � 1 - Select Counter 1 � � ����������������������������Ŀ � 2 - Select Counter 2 � � � Read/Load � ������������������������ � � 0 - Counter Latching � ���������Ĵ 1 - Read/Load LSB only � � 2 - Read/Load MSB only � � 3 - Read/Load LSB then MSB � ������������������������������ ����������������������������������������������������������������������������� � The PIT Modes � ����������������� The PIT is capable of operating in 6 different modes: MODE 0 - Interrupt on Terminal Count ������������������������������������ When this mode is set the output will be low. Loading the count register with a value will cause the output to remain low and the counter will start counting down. When the counter reaches 0 the output will go high and remain high until the counter is reprogrammed. The counter will continue to count down after terminal count is reached. Writing a value to the count register during counting will stop the counter, writing a second byte starts the new count. MODE 1 - Programmable One-Shot ������������������������������ The output will go low once the counter has been loaded, and will go high once terminal count has been reached. Once terminal count has been reached it can be triggered again. MODE 2 - Rate Generator ����������������������� A standard divide-by-N counter. The output will be low for one period of the input clock then it will remain high for the time in the counter. This cycle will keep repeating. MODE 3 - Square Wave Rate Generator ����������������������������������� Similar to mode 2, except the ouput will remain high until one half of the count has been completed and then low for the other half. MODE 4 - Software Triggered Strobe ���������������������������������� After the mode is set the output will be high. Once the count is loaded it will start counting, and will go low once terminal count is reached. MODE 5 - Hardware Triggered Strobe ���������������������������������� Hardware triggered strobe. Similar to mode 5, but it waits for a hardware trigger signal before starting to count. Modes 1 and 5 require the PIT gate pin to go high in order to start counting. I'm not sure if this has been implemented in the PC. ����������������������������������������������������������������������������� � Counter Latching � �������������������� Setting the Read/Load field in the Control Word to 0 (Counter Latch) causes the appropriate channel to go into a sort of "lap" mode, the counter keeps counting down internally but it appears to have stopped if you read it's values through the channel's counter port. In this way you get a stable count value when you read the counter. Once you send a counter latch command you