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A virtual machine for program "archival". The entire body of programs for the V3 architecture can be trivially ported (to a new architecture, or into the future as the system under an existing implementation changes) by only implementing this specification. That implementation can then be used to run all the programs written for V3. The ISA aims to strike a balance between being straight forward to implement, but providing rich enough features to support useful applications, and encoded compactly.
Memory is a contiguous address space of 64k 16-bit cells, which are not byte addressable -- each consecutive address references the next 16-bit cell, and each cell can be a 16-bit machine instruction, a 16-bit operand for the preceding instruction or some other user defined 16-bit data value. Character strings are not packed; instead each consecutive character in a string uses a full 16-bit cell, encoded as UTF-16.
The CPU has a dual stack architecture and several additional registers. The stacks share $1f9 cells between the data stack and the exit stack, all mapped into the same address space, as are the first 6 register contents, for a total of $200 memory mapped cells. Registers %d and %e each refer to the next available empty cell inside the data and exit stacks respectively. These stacks grow towards each other from either end of the shared stack cells. Stack overflow occurs when the top elements collide somewhere between the two extremes, not at an arbitrary "half-way" address.
~~~~~ box-diagram of CPU components and connections
,>,>- - - - - - ->?+-------+?<- - - - .
... | ... | / / | | ^
,-> $1237 | nextop | / / v v REGISTERS
| +--------+ / / src dst +----+----+
| $1236 | arg2 -+' / __v__ __v__ | %a | %b |
| $1235 | arg1 -+-' +----+----+ \ \ / / | | %c-+>-.
| $1234 | opcode-+--->| %i | %f |>--in->\ v / | %d | %e | |
| +--------+ +-v--+----+ ,->\ ALU / | %h | | |
| ... | ... | | / \_____/ | %r | %s | |
| ^ `-----------' v | %t | %n | |
| | dst +----+----+ |
| | v ^ |
| `- - - - - - - - - - - - - - - < +->------------' |
`--------------< %c is the address of the next opcode <---------------'
|ADDRS|<MEMORY>|<- CPU ->|
~~~~~ 16-bit cpu registers
%a address - general purpose register
%b base - general purpose register
%c counter - program counter; address of the next instruction to fetch
%d data - reference to the next empty data stack slot
%e exit - reference to the next empty exit stack slot
%f flag - 1-bit flags set as a side effect of operations
%h height - height of the allocated stack of memory segments
%i instruction - instruction currently being decoded
%m memory - index of the active memory segment
%r return - "return" (top) element on exit stack
%s second - "second" element on exit stack
%t top - "top" element on data stack
%n next - "next" (2nd) element on data stack