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@Assembler Programming Topics :8086 architecture ^Intel 8086 Family Architecture % General Purpose Registers Segment Registers AH/AL AX (EAX) Accumulator CS Code Segment BH/BL BX (EBX) Base DS Data Segment CH/CL CX (ECX) Counter SS Stack Segment DH/DL DX (EDX) Data ES Extra Segment (FS) 386 and newer (Exx) indicates 386+ 32 bit register (GS) 386 and newer % Pointer Registers Stack Registers SI (ESI) Source Index SP (ESP) Stack Pointer DI (EDI) Destination Index BP (EBP) Base Pointer IP Instruction Pointer % Status Registers FLAGS Status Flags (see ~FLAGS~) % Special Registers (386+ only) CR0 Control Register 0 DR0 Debug Register 0 CR2 Control Register 2 DR1 Debug Register 1 CR3 Control Register 3 DR2 Debug Register 2 DR3 Debug Register 3 TR4 Test Register 4 DR6 Debug Register 6 TR5 Test Register 5 DR7 Debug Register 7 TR6 Test Register 6 TR7 Test Register 7 % Register Default Segment Valid Overrides BP SS DS, ES, CS SI or DI DS ES, SS, CS DI strings ES None SI strings DS ES, SS, CS - see ~CPU~ ~DETECTING~ ~Instruction Timing~ :Instruction Timing ^Instruction Clock Cycle Calculation Some instructions require additional clock cycles due to a "Next Instruction Component" identified by a "+m" in the instruction clock cycle listings. This is due to the prefetch queue being purge on a control transfers. Below is the general rule for calculating "m": 88/86 not applicable 286 "m" is the number of bytes in the next instruction 386 "m" is the number of components in the next instruction (the instruction coding (each byte), plus the data and the displacement are all considered components) ^8088/8086 Effective Address (EA) Calculation % Description Clock Cycles Displacement 6 Base or Index (BX,BP,SI,DI) 5 Displacement+(Base or Index) 9 Base+Index (BP+DI,BX+SI) 7 Base+Index (BP+SI,BX+DI) 8 Base+Index+Displacement (BP+DI,BX+SI) 11 Base+Index+Displacement (BP+SI+disp,BX+DI+disp) 12 - add 4 cycles for word operands at odd addresses - add 2 cycles for segment override - 80188/80186 timings differ from those of the 8088/8086/80286 % Task State Calculation "TS" is defined as switching from VM/486 or 80286 TSS to one of the following: ????????????????????????????????????????? ? New Task ? ????????????????????????????????????????? ?????????????????486 TSS?486 TSS?386 TSS?386 TSS?286 TSS? ? Old Task ? (VM=0)? (VM=1)? (VM=0)? (VM=1)? ? ????????????????????????????????????????????????????????? 386 TSS (VM=0) ? ? ? 309 ? 226 ? 282 ? ????????????????????????????????????????? 386 TSS (VM=1) ? ? ? 314 ? 231 ? 287 ? ????????????????????????????????????????? 386 CPU/286 TSS ? ? ? 307 ? 224 ? 280 ? ????????????????????????????????????????? 486 CPU/286 TSS ? 199 ? 177 ? ? ? 180 ? ????????????????????????????????????????? % Miscellaneous - all timings are for best case and do not take into account wait states, instruction alignment, the state of the prefetch queue, DMA refresh cycles, cache hits/misses or exception processing. - to convert clocks to nanoseconds divide one microsecond by the processor speed in MegaHertz: ^(1000MHz/(n MHz)) = X nanoseconds - see ~8086 Architecture~ :directives:asm directives ^Macro Assembler Directives ^Processor Code Generation Directives .186 enables assembly of 80186 instructions .286 enables assembly of non privileged 80286 instructions .286C same as .286 .286P enables assembly of all 80286 instructions .287 enabled assembly of 80287 instructions .386 enabled assembly of non privileged 80386 instructions If used before .MODEL segments are defined as 32bits. Causes all segments to default to DWORD alignment. .386P enabled assembly of all 80386 instructions (see .386) .387 enabled assembly of 80387 instructions .8086 default, enables assembly of 8088/8086 instruction .8087 default, enables assembly of 8087 instructions These directives must precede the segment they are to effect. they cannot occur within a segment. ^Memory Model Directives .CODE [name] starts code segment; must follow .MODEL directive .CONST starts a constant data segment with name CONST; must follow .MODEL directive; placed in DGROUP .DATA starts a near data segment for initialized data with name _DATA; must follow .MODEL directive; placed in DGROUP .DATA? starts a near data segment for uninitialized data with name _BSS; must follow .MODEL directive; placed in DGROUP .FARDATA [name] not placed in any group .FARDATA? [name] not placed in any group .MODEL model defines memory model to be one of the following: SMALL, COMPACT, MEDIUM, LARGE or HUGE; must be used prior to any other segment directive .STACK [size] indicates start of stack segment named 'STACK' with size indicating number of bytes to reserve, default is 1k; placed in DGROUP ^Segment Definition, Segment Ordering and Linkage Directives .ALPHA orders segments alphabetically .SEQ orders segments sequentially (default) ASSUME sreg:name [,sreg:name...] selects default segment register to be used by the assembler, not the CPU, for addressing all symbols in the segment or group. Name must be associated with a SEGMENT or GROUP or set to "NOTHING" to indicate no segment register is to be associated. COMM def [,def...] defines variables that are both public and external (communal). Can be used in and include file to identify it to each source file without declaring it in each model as extern. Actually defines data once. Communal variables cannot be initialized, and are not guaranteed to be allocated contiguously since these are allocated by the linker. DOSSEG orders segments the same as DOS. This is Microsoft languages default order; causes paragph alignment END [name] marks end of source module and sets program start address (CS:IP) if 'name' is present name ENDP ends procedure 'name' name ENDS ends a segment or structure EXTRN name:type [,name:type...] defines one or more external symbols name GROUP seg[,seg] name LABEL [NEAR|FAR|PROC] defines an entry point; If PROC is specified, it's value depends on the current MODEL NAME pgmName ignored since MASM 5.0; used to set module name name PROC [NEAR|FAR] defines procedure; NEAR/FAR has .MODEL default PUBLIC name[,name...] makes symbol 'name' available to other modules name SEGMENT [align][combine][use]['class'] align = BYTE align on byte address (no alignment) = WORD align on even address = DWORD align on DWORD address = PARA align on next 16 byte paragraph = PAGE align on next 256 byte boundary combine = PUBLIC similar named segments are concatenated (CS) = STACK similar named segments are concatenated (SS) = COMMON similar named segment are overlapped = MEMORY similar names segments are concatenated = AT addr segment relative to absolute address = nothing segment is private and loaded independent use = USE16 segments will be 16 bits (if .386) = USE32 segments will be 32 bits (if .386) ^Data Allocation Directives ALIGN n aligns next variable or instruction on a boundary that is a multiple of "n". This can speed memory fetches on 16 and 32 bit CPU'S if aligned. New to ~MASM~ 5.0, previous versions used EVEN. Can result in NOP's added to code. [name] DB init[,init...] define byte [name] DD init[,init...] define double word (DWORD, 4 bytes) [name] DF init[,init...] define far word (FWORD, 386, 6 bytes) [name] DQ init[,init...] define quad word (QWORD, 8 bytes) [name] DT init[,init...] define temp word (TBYTE, 10 bytes) [name] DW init[,init...] define word (WORD, 2 bytes) count DUP (init[,init...]) duplicate 'init' 'count' times; DUP can be nested to 17 levels; DUP'ed initial values of (?) don't result in data in the object file but instead increment the next data addr name ENDS end of structure or segment EVEN same as align 2; Aligns data on even boundary ORG expr sets location counter to 'expr'; If 'expr' is '