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A Proposed Assembly Language Syntax For 65c816 Assemblers by Randall Hyde This is a proposed standard for 65c816 assembly language. The proposed standard comes in three levels: subset, full, and extended. The subset standard is intended for simple (or inexpensive) products, particularly those aimed at beginning 65c816 assembly language programmers. The full standard is the focus of this proposal. An assembler meeting the full level adopts all of the requirements outlined in this paper. The extended level is a mechanism whereby a vendor can claim full compliance with the standard and point out that there are extensions as well. An assembler cannot claim extended level compliance unless it also complies with the full standard. An assembler, no matter how many extensions are incorporated, will have to claim subset level unless the full standard is supported. This ensures that programmers who do not use any assembler extensions can assemble their programs on any assembler meeting the full or extended compliance levels. In addition to the items required for compliance, this proposal suggests several extensions in the interests of compatibility with existing 65c816 assemblers. These recommendations are not required for full compliance with the standard, they're included in this proposal as suggestions to help make conversion of existing programs easier. The suggestions are presented in two levels: recommended and optional. Recommended items should be present in any decent 65c816 package. Inclusion of the optional items is discouraged (since there are other ways to accomplish the same operation within the confines of the standard) but may be included in the assembler at the vendor's discretion to help alleviate conversion problems. 65c816 Instruction Mnemonics ---------------------------- All of the following mnemonics are required at the subset, full, and extended standard levels. The following mnemonics handle the basic 65c816 instruction set: ADC - add with carry AND - logical AND BCC - branch if carry clear BCS - branch if carry set BEQ - branch if equal BIT - bit test BMI - branch if minus BNE - branch if not equal BPL - branch if plus BRA - branch always BRK - break point instruction BVC - branch if overflow clear BVS - branch if overflow set CLC - clear the carry flag CLD - clear the decimal flag CLI - clear the interrupt flag CLP - clear bits in P CLR - store a zero into memory CMP - compare accumulator CPX - compare x register CPY - compare y register CSP - call system procedure DEC - decrement acc or memory DEX - decrement x register DEY - decrement y register EOR - exclusive-or accumulator HLT - halt (stop) the clock INC - increment acc or memory INX - increment x register INY - increment y register JMP - jump to new location JSR - jump to subroutine LDA - load accumulator LDX - load x register LDY - load y register MVN - block move (decrement) MVP - block move (increment) NOP - no operation ORA - logical or accumulator PHA - push accumulator PHP - push p PHX - push x register PHY - push y register PLA - pop accumulator PLP - pop p PLX - pop x register PLY - pop y register PSH - push operand PUL - pop operand RET - return from subroutine ROL - rotate left acc/mem ROR - rotate right acc/mem RTI - return from interrupt RTL - return from long subroutine RTS - return from short subroutine SBC - subtract with carry SED - set decimal flag SEI - set interrupt flag SEP - set bits in P SHL - shift left acc/mem SHR - shift right acc/mem STA - store accumulator STX - store x register STY - store y register SWA - swap accumulator halves TAD - transfer acc to D TAS - transfer acc to S TAX - transfer acc to x TAY - transfer acc to y TCB - test and clear bit TDA - transfer D to acc TSA - transfer S to acc TSB - test and set bit TSX - transfer S to X TXA - transfer x to acc TXS - transfer x to S TXY - transfer x to y TYA - transfer y to acc TYX - transfer y to x WAI - wait for interrupt XCE - exchange carry with emulation bit Comments: CLP replaces REP in the original 65c816 instruction set, since CLP is a tad more consistent with the original 6502 instruction set. See "recommended options" for the status of REP. CLR replaces the STZ instruction. Since STA, STX, and STY are used to store 65c816 registers, STZ seems to imply that there is a Z register. Using CLR (clear) eliminates any confusion. CSP (call system procedure) replaces the COP mnemonic. COP was little more than a software interrupt in both intent and implementation. CSP helps make this usage a little clearer. HLT replaces the STP mnemonic. STP, like the STZ mnemonic, implies that the P register is being stored somewhere. HLT (for halt) is just as obvious as "stop the clock" yet it doesn't have the same "look and feel" as a store instruction. JML and JSL are not really required by the new standard; but see recommended options concerning these two instructions. Most of the new 65c816 push and pull instructions have been collapsed into two instructions: PSH and PUL. PEA label becomes PSH #label PEI (label) becomes PSH label PER label becomes PSH @label PHB becomes PSH DBR PHD becomes PSH D PHK becomes PSH PBR PLB becomes PUL DBR PLD becomes PUL D These mnemonics are more in line with the original design of the 6502 instruction set whereby the mnemonic specifies the operation and the operand specifies the addressing mode and address. The RET instruction gets converted to RTS or RTL, depending on the type of subroutine being declared. RTS and RTL still exist in order to force a short or long return. SHL and SHR (shift left and shift right) are used instead of ASL and LSR. The 6500 family has NEVER supported an arithmetic shift left instruction. The operation performed by the ASL mnemonic is really a logical shift left. To simplify matters, SHL and SHR are used to specify shift left and shift right. SWA (swap accumulator halves) is used instead of XBA. Since this is the only instruction that references the "B" accumulator, there's no valid reason for even treating the accumulator as two distinct entities (this is just a carry-over from the 6800 MPU). Likewise, since the eight-bit accumulator cannot be distinguished from the 16-bit accumulator on an instruction by instruction basis (it depends on the setting of the M bit in the P register), the accumulator should always be referred to as A, regardless of whether the CPU is in the eight or sixteen bit mode. Therefore, instructions like TCD, TCS, TDC, and TSC should be replaced by TAD, TAS, TDA, and TSA. For more info on these new mnemonics, see the section on "recommended options". Built-in Macros --------------- The following instructions actually generate one or more instructions. They are not required at the subset level, but are required at the full and extended levels. ADD - emits CLC then ADC BFL - emits BEQ (branch if false) BGE - emits BCS BLT - emits BCC BTR - emits BNE (branch if true) BSR - emits PER *+2 then BRA (short) or PER *+3 then BRL (long) SUB - emits SEC then SBC Recommended Options ------------------- The following mnemonics are aliases of existing instructions. The (proposed) standard recommends that the assembler support these mnemonics, mainly to provide compatibility with older source code, but does not recommend their use in new programs. Some (or all) of these items may be removed from the recommended list in future revisions of the standard. None of these recommended items need be present at the subset level. If these are the only extensions over and above the full syntax, the assembler CANNOT claim to be an extended level assembler. ASL BRL COP JML JSL LSR PEA PEI PER PHB PHK PHK PLB PLD REP TCD TCS TDC TSC TRB WDM XBA Symbols, Constants, and Other Items ----------------------------------- Symbols may contain any reasonable number of characters at the full level. At the subset compliance level, at least 16 characters should be supported and 32 is recommeded. A "reasonable" number of characters should be at least 64 if the implementor needs a maximum value. Symbols must begin with an alphabetic character and may contain (only) the following symbols: A-Z, a-z, 0-9, "_", "$", and "!". The assembler must be capable of treating upper and lower case alphabetic characters identically. Note that this does not disallow an assembler from allowing the programmer to choose that upper and lower case be distinct, it simply requires that in the default case, upper and lower case characters are treated identically. Note that the standard does not require case sensitivity in the assembler (and, in fact, recommends against it). Therefore, anyone foolish enough (for many, many reasons) to create variables that differ only in the case of the letters they contain is risking port- ability problems (as well as maintenence, readability, and other problems). The following symbols are reserved and may not be redefined within the program: A, X, Y, S, DBR, PBR, D, M, P Nor may these symbol appear as fields to a record or type definition (which will be described later). Constants take six different forms: character constants, string constants, binary constants, decimal constants, hexadecimal constants and set constants. Character constants are created by surrounding a single character by a pair of apostrophes or quotation marks, e.g., "s", "a", '