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Newsgroups: comp.sys.apple2.programmer
Subject: Re: SSC info wanted (again)
Message-ID: <s04y7B4w165w@qedbbs.com>
From: quor@qedbbs.com (Matthew Ghio)
Date: 20 Jul 93 06:37:51 GMT
Sender: bbs@qed.UUCP
References: <199307152147.AA18084@ghostwheel.bga.com>
Organization: The QED BBS, Lakewood CA
Lines: 96
khym@ghostwheel.bga.com (Dave Huang) writes:
> OK, try #3.. if this doesn't work I'll have to steal someone's NNTP
> server :-) (and apologies if you've seen this before :)
>
> I was wondering, what do $C088 + n0 through $C08B + n0 on a Super
> Serial Card do?
Ok, here's something I dug up from my archives (you're not the first person to ask that question)...
-------------------------------------------------------------------------------
Programming the Apple Super Serial Card and compatible serial interfaces:
These docs brought to you by Quor, March 27, 1993.
The SSC has four registers beginning at $C088 plus the slot number of the SSC multiplied by 16. They are described below:
$C0x8: Send/receive register
When a byte is received, it is placed in this register, and can be read. Writing a byte to this register sends it out.
$C0x9: Status Register (read only)
bit 0: This is set when a parity error has been detected.
bit 1: This is set when a framing error has been detected.
bit 2: This is set when an overrun occured (data was not read and has been
lost)
bit 3: This is set when a new byte has been received and is waiting in the
receive register.
bit 4: This is set when the transmit register is empty, and therefore is ready
to send another byte.
bit 5: This reports the status of the data carrier detect (DCD)
bit 6: This reports the status of the data set ready (DSR)
bit 7: This is set when an interrupt (IRQ) was generated by the SSC
$C0xA: Command register (read/write)
bit 0: Setting this bit turns on the Data Terminal Ready
bit 1: Setting this bit will cause an interrupt to be generated every time a
byte is received.
bits 2&3: Control the transmitter as follows:
bit 2 bit 3
0 0 transmit interrupt disabled, RTS high, transmitter off
0 1 transmit interrupt disabled, RTS low, transmitter on
1 0 transmit interrupt enabled, RTS low, transmitter on
1 1 transmit interrupt disabled, RTS low, transmit break
bit 4: If this bit is set, and bits 2 and 3 are both zero, all data received
will automatically be echoed back to the sender.
bits 5-7: If bit 5 is set, parity will be checked and transmitted besed on the
following settings of bits 6 & 7:
bit 6 bit 7
0 0 odd parity transmitted and checked
1 0 even parity transmitted and checked
0 1 mark transmitted, no check
1 1 space transmitted, no check
$C0xB: Control register
bits 0-3: Baud rate:
bit 3 bit 2 bit 1 bit 0
0 0 0 0 Use external clock
0 0 0 1 50 bps
0 0 1 0 75 bps
0 0 1 1 109.92 bps
0 1 0 0 134.58 bps
0 1 0 1 150 bps
0 1 1 0 300 bps
0 1 1 1 600 bps
1 0 0 0 1200 bps
1 0 0 1 1800 bps
1 0 1 0 2400 bps
1 0 1 1 3600 bps
1 1 0 0 4800 bps
1 1 0 1 7200 bps
1 1 1 0 9600 bps
1 1 1 1 19200 bps
bit 4: Receiver clock source. When set (1), use baud rate generator, when
clear (0), use external clock
bits 5-6: Word legnth:
bit 6 bit 5
0 0 8 bits
0 1 7 bits
1 0 6 bits
1 1 5 bits
bit 7: If clear, send one stop bit, if set, send two.
Final note: On the Apple SSC, $C0x1 and $C0x2 report the status of the DIP switches on the card.
Newsgroups: comp.sys.apple2.programmer
Path: blue.weeg.uiowa.edu!news.uiowa.edu!uunet!comp.vuw.ac.nz!actrix.gen.nz!dempson
From: dempson@actrix.gen.nz (David Empson)
Subject: Re: Need info re accessing serial card
Message-ID: <CtyK8t.4wH@actrix.gen.nz>
Organization: Actrix Information Exchange
References: <312eat$ls0@nic-nac.csu.net> <CtLMtG.246@actrix.gen.nz> <31cfcr$orr@kodak.rdcs.Kodak.COM> <Cttr07.3vz@griffin.cuc.ab.ca>
Date: Wed, 3 Aug 1994 12:05:16 GMT
Lines: 103
In article <Cttr07.3vz@griffin.cuc.ab.ca>,
Sean Dockery <dockery@griffin.cuc.ab.ca> wrote:
>
> I always thought that the DIP switch on the SSC was similar to the power
> bar concept for your computer: It doesn't prevent you enabling interrupts
> through software when it is OFF (power bar OFF, computer ON), but it also
> doesn't force you to enable interrupts when it is ON (power bar ON,
> computer OFF). Someone please correct me if this is not the case.
Sorry, but that isn't correct. The interrupt enable switch (SW2-6)
must be ON for any interrupts to get through from the ACIA. It
disconnects the IRQ line if it is OFF.
Some of the ACIA's interrupt sources (DSR and DCD change) cannot be
disabled through software if you want to use the serial card (they are
disabled if the DTR output of the ACIA is turned off, but that disables
the whole chip). If the interrupt switch was on and you enabled the
DTR line (e.g. PR#2), any change on DSR or DCD would crash unless you
had an interrupt handler to catch it.
See my other posting on this thread for further details.
> Hmmm... I don't see the problem why everyone is so concerned about
> unlikely (or impossible) interrupts. Consider:
>
> The 6551 is only generating interrupts during the following situations when
> both receipt and transmission interrupts are enabled:
>
> o receipt register full
> o transmission register full
> o DCD state change
> o DSR state change
>
> The first two can be explicitly disabled on the 6551 through software.
>
> The third one will only occur if you are online and your host hangs up on
> you, or if you have your modem set to auto-answer and someone phones in
> with a modem carrier.
>
> The last one won't ever occur if you are not transmitting.
Either DCD or DSR may change state if you unplug the modem, or switch
it on/off.
> Remember the following two quirks about the 6551 as well:
>
> o You cannot send if you have the DTR signal set to false.
You can't do ANYTHING - it turns off everything in the chip (all
interrupt sources, transmit and receive).
> o You cannot receive if the DCD signal is false.
You also cannot transmit if RTS is turned off.
> CONTROL REGISTER ($C08B + $n0)
> 4 - receiver clock source
> 0 = external receiver clock
Don't use this setting on the SSC - there is no external receiver clock.
> 3210 - internal baud rate generator
> 0 0 0 0 = external receiver clock x 16
Don't use this setting on the SSC - it only works if the ACIA is being
clocked by a square wave input, not a crystal.
> COMMAND REGISTER ($C08A + $n0)
> 32 - transmitter controls (RTS signal)
> 0 0 = transmit IRQ disabled, RTS high
That is "transmitter AND transmit IRQ disabled, RTS high"
> STATUS REGISTER ($C089 + $n0)
> 7 - IRQ pending status
> 0 = no interrupt
> 1 = interrupt has occurred
Be very careful when reading the status register with interrupts
enabled: if the IRQ bit is set, it is cleared by reading this
register. This means, for example, if you you are are using receive
interrupts but are polling the status register to detect when you can
next transmit a character, you may cause an IRQ to be lost if it
happens to be read by the transmit routine first.
To avoid this, you must check the IRQ flag whenever this register is
read.
This is really only a problem if you're relying on the IRQ
flag to detect an interrupt from the SSC - the interrupt will still
occur, but the interrupt handler will not see the IRQ flag set. If it
is a receive or transmit interrupt, there is a separate flag you can
check, but you cannot identify a state change interrupt for DCD or DSR
unless the IRQ bit is set. You can save the previous state for DCD
and DSR, but a three-way toggle on one of the lines may cause two
interrupts but go undetected.
--
David Empson
dempson@actrix.gen.nz
Snail mail: P.O. Box 27-103, Wellington, New Zealand