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This message was originally submitted by delaneyg@WNRE.AECL.CA to the APPLE2-L list at BROWNVM. If you simply forward it back to the list, it will be distributed with the paragraph you are now reading being automatically removed. If you edit the contributions you receive into a digest, you will need to remove this paragraph before mailing the result to the list. Finally, if you need more information from the author of this message, you should be able to do so by simply replying to this note. ----------------- Message requiring your approval (45 lines) ------------------ Split Cache Modification for the ZipGSX DISCLAIMER: Any modifications made to the ZipGSX product that deface, damage, or alter the product may invalidate any existing warranty. Zip Technologies may deny warranty coverage for any product received with modifications made outside the direction of Zip Technologies. In this case, nominal services charges would apply for whatever services are required. What Is A "Split Cache"? The processor makes accesses to memory that are for either the executing program code or the data being accessed by the code. Some of the accesses from the processor are for the program code that is running. The other accesses are for the data being use d by the executing program. In a normal cache memory archetecture, both the program code and the data are treated with no distinction. Both code and data reside within the cache memory array and are thus both accellerated. A split cache simply divides the cache memory into two separate sections reserving one for the program code, and the other for the data accessed by the code. The program code will reside in one reserved section of the cache memory. The data will reside in a separate isolated section of the cache memory. Depending on the application type, this can cause a marked increase in the performance of the cache memory. On the other hand, a degradation of performance can occur for some applications inhibited by the reduced cache size for the program code or the data. How Does a Split Cache Help Performance? As an example, in a 16K cache system, there is 16K of memory which can be used freely for code or data. There are no restrictions besides the total amount of memory available. The cache can hold up to 16K of data o r up to 16K of program code, or any combination of the two adding up to 16K. If a program is moving a large data block, the program code executing may be displaced by the data that is being moved. When this happens, the program code must be reloaded into t he cache memory and will cause performance to diminish. By splitting the 16K cache, there are two separate 8K cache sections. One section is only for code and the other is only for data. The effective size of the cache memory is reduced to 8K, even though the total amount of cache memory remains at 16K. By se parating the two sections in this way, program code can be isolated from large data blocks. In the case of the large data transfer described above, the program code is not displaced by the data since the data activity is occuring in a physically separate s