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Babar Khan
Type devroom
Starts on day 1 (2021-02-06) at 17:15 (Brussels time, UTC+1) in room Hardware trusted (duration 00:25)
Matrix room #hardware trusted:fosdem.org
Hardware accelerators are being increasingly integrated into today’s heterogenous computing systems to achieve improved performance. However, the resulting heterogenous hardware also increases the challenge to ensure the security of these accelerators.
High-Level Synthesis (HLS) automates the creation of a register transfer level (RTL) description of a digital circuit starting from its high-level specification (e.g., C/C++/SystemC). In this talk, I would like to discuss different extensions and methodologies to High-Level Synthesis (HLS) compilers for generating secure accelerators. Precisely addressing the HLS vulnerabilities like side-channel listed in Common Weakness Enumeration (CWE) list.