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Ali Hajiabadi
Type devroom
Starts on day 1 (2021-02-06) at 10:00 (Brussels time, UTC+1) in room Hpc (duration 00:30)
Matrix room #hpc:fosdem.org
With the end of Moore’s law, improving single-core processor performance can be extremely difficult to do in an energy-efficient manner. One alternative is to rethink conventional processor design methodologies and propose innovative ideas to unlock additional performance and efficiency. In an attempt to overcome these difficulties, we propose a compiler-informed non-speculative out-of-order commit processor, that attacks the limitations of in-order commit in current out-of-order cores to increase the effective instruction window and use critical resources of the core more intelligently. We build our core based on the open source RISC-V ISA. The hardware and software ecosystem around RISC-V enables building custom hardware and experimenting new HW/SW cooperative ideas.