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I have wired and soldered and generally butchered this poor 8-bit micro, and it's now better than new. Honest!
So, in reality, I have dabbed a bit of solder onto three pins on two chips to attach three wires. I had the idea of using breadboard jumper wires, snipping them in half, soldering the wires to their target chips, then plugging their male end into their female end.
So, now I can remove and add RAM/ROM chips without any further soldering. All very undoable, with no lasting damage.
I currently have a 32K EPROM with the MFFS filing system in one half, and BASIC in the other. This replaces two 16K ROMS thanks to the wiring up of the A14 pin to the ROM Select Register.
I also now have a 32K SRAM chip that provides two 16K banks of what looks like ROM to the BBC, but which, since it's really RAM, can be written to. Although I had instructions, they came with no explanation, so I didn't do anything until I knew exactly what was happening. Just for fun really, but I admit I don't like following instructions blindly.
The 7400 series of TTL chips must have been like Lego to hardware designers of the day. We get so much in a single package these days. Even a humble PIC chip or AVR has masses of stuff incorporated - IO Ports, UARTs, RAM, EEPROM, Timers, etc., and of course a CPU. They even have their own built in oscillators.
The BBC Micro has these things built from separate ICs. The two that I was concerned with were the 74LS163 (TTL Synchronous binary counter with preset), and the 74LS139 (TTL dual 2-to-4 decoder/latch).
The 74LS163, although also a counter, is used simply as a register - essentially you set the input pins (P0 to P3), and from the next clock cycle onwards the output pins (Q0-Q3) will hold those values until you change them again.
The 74LS139 is a decoder that takes inputs on two pins (so four possible values, 0-3), and sets one of four output pins accordingly. Again, it will hold the output pins indefinitely, until you change the inputs. It's a dual 2-to-4 decoder, so there are actually two that work independently in the same chip package.
So the 74LS163 and the 74LS139 work in tandem to decode a ROM number (0-3, since there are four ROM sockets) into a Chip-Enable signal for each ROM. You set the 74LS163 register to, for example, zero, then the decoder will set the first pin of its four outputs. Set the register to 3 (binary 11), then the fourth pin of its four outputs will be set, and these outputs are wired directly to the chip enable pin on the ROM sockets.
What a waste of two bits! There are 16 possible values in the register, yet only four values are used to decode ROMS. This makes sense, because there are only four ROM sockets, but we can use the other two register output bits to control the high bit of each chip's address lines to address more memory within a single chip.
This is how I got access to the lower bank in the 32K EEPROM I was sent. While A14 is normally pulled high, by bending the pin up and connecting it instead to one of the unused pins of the 74LS163 register (Q2 or Q3), then when Q0 and Q1 select my EEPROM, Q2 or Q3 (whichever I chose to wire up) selects the upper or lower 16K space.
Exactly the same is done for the SRAM chip. The A14 pin is one of two pins that differs from the EEPROM chip, so it can't be connected to the socket anyway. It's almost a free enhancement.
An EEPROM doesn not have a write-enable, naturally, since it is ROM. The SRAM requires it, otherwise we'd have no way to write data to the chip. I knew from the instruction where to wire it, but it bugged my that I didn't know why. There are R/nW (active-low write) signals all over the board. This is the same signal used for the DRAM. Why was this specific pin chosen?
Actually there are three pins that can be used, but they're really all just different points on the same wire. There was no clear answer, but the schematics gave a strong clue.
The signal to drive the SRAM's Write-Enable is essentially the CPU's R/W signal passed through an AND gate with the 2MHz clock. This part of the circuit derives both a R/W and a NOT R/W from the R/W signal that transitions with the clock. One signal is always the opposite of the other, and they can never both be high or both be low. They seem to drive chips that have both Read and Write pins, and the SRAM is one such device. It has Output Enable and Write Enable. Output Enable configures the SRAM data pins as outputs. Write-Enable configures them as high-impendance inputs. The chip's data pins are never configured as both input and output simultaneously.
So I wired it up.
I'm thinking about adding a battery backup to the SRAM chips. Or more accurately, I'm thinking about the simplest and least intrusive way to do it.
My simplest idea is to use 3 AA batteries, with a weak pullup resistor between the +ve and the chip-enable (which is active low). Then bend the SRAM's Vcc pin and wire it to the PSU Vcc via a diode, and similarly wire the battery +ve to the SRAM's Vcc. As long as the chip-enable doesn't sink current, then it should work. I don't know enough about 7400 series chips generally to be sure, much less chips from the 80s.
A case of try it and see.
My description of this page on the (shock!, horror!) web.
A list of all BBC Micro chips, and their functions.
A wiki page on BBC Micro Paged ROMs.
stardot.org forum post on SRAM.
My original post on my new BBC Micro