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This is the first time someone at least make some sense of the whole M1 Max Chiplet theory / hypothesis. That there is an interconnect ready. Unlike all previous comments there people suggest they magically stack 2 - 4 SoC together.
The TSMC MCM interposer size is the same as 4x M1 Max Die Size. Should they choose that route at a potential of 500W+ TDP Design.
Still doesn't solve NUMA issue though. Along with GPU access. This is basically the same design as Zen 1. It was the whole reason why there is an IOD in the middle with Zen 2 and above. And I hope Apple has something clever to show the word why Zen 1 failed and they succeed.
On the GPU I am thinking something from PowerVR [1] if it works as advertise. I just wish we could get more information soon.
[1]
https://www.anandtech.com/print/16155/imagination-announces-...
In what universe did Zen 1 fail? Zen 1 was one of the best-performing designs in the world and scaled very well to high core counts.
The fact that Zen 2 is better doesn't reduce the excellence of Zen 1.
>In what universe did Zen 1 fail?
Failed in the context of NUMA, not the product or uArch. Which is _still_ an issue with Zen 2. Only better managed.
There might be an I/O die. I'd go so far as to say it could even be an I/O die with a bunch more cache too.
Subtitled: Person tweets rumour with zero evidence and becomes runaway tweet storm - oh wait, that isn’t what happened
Looks like a provision for some kind of EMIB like interconnect.