💾 Archived View for dioskouroi.xyz › thread › 29378165 captured on 2021-11-30 at 20:18:30. Gemini links have been rewritten to link to archived content

-=-=-=-=-=-=-

A Transparent Wishbone-to-SPI Bridge Supporting Execute-in-Place (XIP)

Author: _quarks_

Score: 16

Comments: 4

Date: 2021-11-29 10:20:03

Web Link

________________________________________________________________________________

supahfly_remix wrote at 2021-11-29 13:10:44:

What is the performance impact of execute-in-place? Does a CPU executing instructions out of external RAM offer enough performance to be worthwhile?

pjc50 wrote at 2021-11-29 13:43:35:

This allows you the possibility of booting directly out of the SPI, where you put a first-stage bootloader that copies the rest of the system into RAM.

Lots of systems do this already by means of mask ROM bootloaders; some people might not want a fixed payload provided by someone else to be the first thing that executes. On the other hand, executing out of SPI is very interceptable.

supahfly_remix wrote at 2021-11-30 12:18:33:

Thank you for the explanation.

outsomnia wrote at 2021-11-29 10:27:08:

Nice missing piece of the RISC-V ecosystem puzzle.