Aucbvax.4596
fa.works
utzoo!decvax!ucbvax!works
Wed Oct 21 23:43:06 1981
WORKS Digest V1 #21
>From JSol@RUTGERS Wed Oct 21 23:02:58 1981
WorkS Digest          Thursday, 22 Sep 1981        Volume 1 : Issue 21

Today's Topics:	      
             Other Considerations Of 32 Bit Processors
		       Videodisks As Memory
----------------------------------------------------------------------

Date: 21 Oct 1981 1918-PDT
From: SCHIFFMAN at SRI-KL
Subject: Addition to processor taxonomy

In my consideration of the "32-bitness" of CPUs, I now realize that I
left out two other things that have a width:

	4) The number of physical address bits presented to the
	   memory bus.  
	   Obviously physical address bits cost more IC pins and
	   backplane wires, contributing to cost.  Not so obviously,
	   address bits can contribute greatly to the cost of memory
	   management hardware (and the time cost of using it).  The
	   point is that you don't really want to pay much more for
	   physical address bits than you need to address the memory
	   your systems will be able to afford.

	5) The internal "name-space" of the architecture, i.e. log2 of
	   the number of unique objects that can be referenced.
	   The reason why we can't more simply define this
	   (as say, the number of bits in a `pointer') is that
	   some architectures can have arbitrarily complex ways
	   of encoding internal names, say by using the data-type
	   field of an op-code to provide extra "logical-address
	   bits".
	   Again, a large name space can be a mixed blessing.  One of
	   the most important (for instruction encoding efficiency)
	   areas of CPU architecture is how to compress memory 
           requirements for expressing local names.  This can be done
	   badly for machines with even a relatively small name space
	   (i.e. the PDP-11, where all offsets take 16 bits).

Under these additional criteria, the updated table...

                             WIDTH (Bits)
CPU		Registers	ALU	Memory	Phys.	Log.
					Data	Addr	Addr
------------------------------------------------------------

Z8000		64,32,16,8	16	16	24	24

MC68000		32		32	16	24	24

I8086		16,8		16	16	20	20

I8088		16,8		16	8	20	20

NS16000		32		32	16	24	24

iAPX-432	to 80		80?	16	24	40
____________________________________________________________

I reread the 43203 data sheet and decided that the memory data bus
was, by the definition that I gave, not "user-supplied", but 16 bits.
The reason for this confusion is that the data bus operates in burst
mode (only one address output for the transaction) for operations on
words longer than 16 bits; this is real optimization since addresses
usually take as much as half a bus cycle.

-Allan

------------------------------

Date: 21 October 1981 2333-EDT (Wednesday)
From: Stephen.Hancock at CMU-10B
Re:   Rotating Memories ("video disks")

The October issue of Mini-Micro-Systems has an artice entitled
"Rotating- memory devices move to optical reading".  The article
informs us that  european systems are being devoloped by Philips NV
and Thomson-CSF.  The device is supposed to be a 10G bit drive with a
twelve inch platter.  There are plans to have a system with a 64
platter magazine (thats 640G bits).  The system is expected to be
released in about 2 years the projected OEM cost is between $2000 and
$10000 each. The article also points out the sales dollar volume and
number of optical units sold will be only a small fraction of the
total rotating memory market.

						Steve

------------------------------

End of WorkS Digest
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